1. Field of the Invention
The present invention relates to a lateral DMOS transistor.
2. Description of the Background Art
A DMOS transistor is understood to be a field-effect transistor with a source region, a channel region, and a drain region, in which the drain region is separated from the channel region by a drift region. Whereas the conductivity of the channel region is controlled by a gate voltage, by which an occurrence and strength of an inversion of the concentrations of positive or negative charge carriers below the gate are controlled, the charge carrier concentration in the drift region is substantially constant, so that in approximate terms an ohmic conductivity results there. The voltage drop occurring during the operation of the transistor across the drift region reduces the portion of the drain-source voltage, emerging via the channel, which leads to an increased transistor breakdown voltage.
In a lateral DMOS transistor, the current flow and the channel region are oriented substantially parallel to the surface of the wafer, whereas in a vertical DMOS transistor it is oriented substantially in direction of a perpendicular to the wafer surface. The lateral DMOS transistor can therefore be contacted from one side, whereas the vertical DMOS transistor must be connected from two sides of the wafer.
DMOS transistors are frequently used as driver transistors for driving inductive loads, particularly in the automotive field, and should have as high a breakdown voltage as possible with a simultaneously minimal space requirement. To avoid edges and corners where locally undesirably high field strengths could arise due to the electrical peak effect, it is known per se to produce DMOS transistors with the aforementioned features and thereby with a stadium structure. In the conventional stadium structure, a distance between the first dielectric structure, which is generally called a field region, and the boundary line along the straight sections is precisely as large as along the curved sections. Although high breakdown voltages can already be realized with a small size with use of stadium structures, the need continues to exist for further optimization of the relation between breakdown voltage and size, in order to further reduce the area of the DMOS transistors and to lower manufacturing costs.
In an alternative approach, a lithographic patterning of the drift region in the curved peripheral regions was used to reduce the doping in these areas. However, element simulations and electrical measurements have shown that the breakdown voltage of the drift region is optimal at a specific doping and declines for higher and lower dopings. This depends on the so-called RESURF (Reduced Surface Field) effect, which contributes substantially to a high breakdown voltage of the element. This effect cannot be utilized optimally both for too low and too high dopings of the drift region.